Verilog Hdl: A Guide To Digital Design & Synthesis
- 2
- Noida: Pearson, 2003.
- ill., 490 p.
Written for both experienced students and newcomers, it offers broad coverage of Verilog HDL from a practical design perspective. One step at a time, Samir Palnitkar introduces students to gate, dataflow (RTL), behavioral, and switch level modeling; presents the Programming Language Interface (PLI); describes leading logic synthesis methodologies; explains timing and delay simulation; and introduces many other essential techniques for creating tomorrows complex digital designs. Palnitkar offers a wealth of proven Verilog HDL modeling tips, and more than 300 fully-updated illustrations, examples, and exercises. Each chapter contains detailed learning objectives and convenient summaries. For Sale in Indian subcontinent only
NEW ?Fully updated for the latest versions of Verilog HDL. Broad coverage, from the fundamentals to the state-of-the-art?Logically progresses from basic techniques for building and simulating small Verilog models to advanced techniques for constructing tomorrow and amp;s most sophisticated digital designs. Extensive examples, illustrations, and exercises? Illuminates every aspect of Verilog HDL design with practical examples and hands-on exercises. Learning objectives and summaries in every chapter? Includes many features designed to promote easier learning and deeper mastery. CD-ROM?SILOS III simulation environment by Simucad, Inc.